Implementing a VHDL design that will display the number of days in a month. The circuit will begin by displaying the number of days in January and cycle through a display of the number of days in the 11 remaining months. This 12 month cycle will then repeat until disabled. This design will have a minimum of two inputs (leap year, start/stop) and be able to display the number of days in the month as well as indicate the current month. One additional user selectable feature should also be implemented. Implementing a VHDL Design to Display the Number of Days in a Month

Implementing a VHDL Design to Display the Number of Days in a Month

VHDL (VHSIC Hardware Description Language) is a powerful language used for designing digital systems such as FPGAs and ASICs. In this case, a VHDL design will be implemented to display the number of days in a month. The design will begin by displaying the number of days in January, then cycle through the remaining eleven months, before repeating the twelve-month cycle until disabled. The circuit will have a minimum of two inputs – a leap year input, and a start/stop input. The output will be able to display the number of days in each month, and indicate the current month. An additional user-selectable feature should also be implemented. To implement the circuit, the Vivado software and Basys3 hardware will be used. With Vivado, implementing the VHDL design should be straightforward. According to Zhejiang Univ. (2016), “Vivado provides an integrated environment for designing with Xilinx FPGAs and Zynq SoCs.” Thus, it should be a perfect tool for implementing the circuit. Furthermore, Basys3 hardware is “an entry-level FPGA board designed exclusively for the Vivado Design Suite” (Digilent Inc., 2021). With these two tools, the. Cont…